The Witcher 3 and Stray can now run on a 64-core RISC-V processor

url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url, url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url url

In the world of modern computer architectures, the vast majority of people today will only interact with Arm or x64_64. There are other architectures, but none that are really as widely used in everyday life. However, an architecture called RISC-V has gained prominence over the years. It is an open standard ISA that anyone can modify and implement, making it a particularly interesting architecture that could challenge Arm in the long run. Now, the developers of Box64 have managed to The Witcher 3 runs on a RISC-V CPU with an AMD Radeon RX550.



Development is progressing rapidly

It uses Box64, Wine and DXVK

The Box64 developers have been working hard over the last year to get Box64 running entirely on RISC-V. According to lead developer ptitSeb, Box64 is both a translation layer and an emulator. He told me the following:


There is the system library translation layer that converts calls from x86_64 ABI to the native version. But there is also the emulation part with all x86_64 binaries (and unpackaged libraries) translated to native code on the fly. The emulation of the x86_64 code needs to be as close to reality as possible (since some encryption/obfuscation tools rely on exact opcode behavior).

What is certain is that there is no “full machine emulation”. No hardware emulation, no special timing, nothing like that. It is limited to CPU emulation, as it is a “use space” emulation and provides the program with a virtual x86_64 Linux environment.


The same concept applies here for the RISC-V version. The Witcher 3 runs on a combination of translation and emulation, which allows it to run at an acceptable framerate on a 64-core RISC-V board. The RISC-V cores of the Milk-V Pioneer are quite weak (but still better than those of the Milk-V Mars), but the point is that it factoriesand it opens the door for more games in the future. Original development (when the developer first Stardew Valley Work on the StarFive VisionFive2 began.


What Strayingit runs on the same machine that the developer got The Witcher 3 runs. It also runs slowly, but since it's an Unreal Engine 4 game, getting it to run is a huge step forward. If Stray becomes fully playable, it's likely that it would improve the performance of other Unreal Engine games as well.

How The Witcher 3 runs on RISC-V

It is very, very complex

The Witcher 3 menu shows that it runs on RISC-V

Source: Box64

To run applications compiled for the x86_64 architecture, Box64 uses Dynarec, an acronym for dynamic recompilation. x86_64 is a CISC (Complex Instruction Set Computer) architecture, which provides a large set of complex instructions that can perform tasks such as memory operations and arithmetic in a single instruction. RISC-V, on the other hand, follows the RISC (Reduced Instruction Set Computer) philosophy and provides a simpler, streamlined instruction set. This difference means that x86_64 code, with its complex instructions, must be translated into sequences of simpler RISC-V instructions.


This process of converting x86_64 code to RISC-V instructions is handled by Dynarec Box64. In this system, ptitSeb explains, blocks of x86_64 instructions are translated into equivalent RISC-V instructions at runtime. These blocks, called “dynablocks,” are then stored and reused when the same x86_64 code is encountered again, reducing the need for repeated translations and improving overall efficiency. For example, if you have a sequence of x86_64 opcodes, a dynablock is an associated sequence of RISC-V opcodes that perform the same logic.


This translation brings with it a number of problems. x86_64 can perform complex operations in a single instruction, while RISC-V requires several simpler instructions to achieve the same result. For example, tasks such as loading data from memory and performing calculations in RISC-V must be broken down into multiple steps. In addition, translating features such as x86_64's flags into RISC-V instructions requires additional effort, since RISC-V has no flags at all.

Currently, RISC-V translation is still in its infancy, but the architecture as a whole is continually evolving. As more and more hardware based on it comes out and developers spend more and more time on it, it's becoming more and more likely that development will eventually gain momentum. While it won't power a handheld gaming PC or anything like that anytime soon, it's certainly improving.


Leave a Comment